As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite a decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. The principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
Conventional stacked capacitor DRAM arrays utilize either a buried bit line or a non-buried bit line construction. With buried bit line constructions, bit lines are provided in close vertical proximity to the bit line contacts of the memory cell field effect transistors (FETs), with the cell capacitors being formed horizontally over the top of the word lines and bit lines. With non-buried bit line constructions, deep vertical contacts are made through a thick insulating layer to the cell FETs, with the capacitor constructions being provided over the word lines beneath the bit lines.
This invention arose out of concerns associated with forming bit line over capacitor arrays of memory cells, and particularly to a simultaneous etch of certain contact openings relative to both peripheral and memory array regions of such circuitry. The invention was motivated to making improvements for such contact etching relative to bit line over capacitor array circuitry of the parent application from which this patent application ultimately matured. However, the artisan will appreciate applicability of the developed technology to a other of semiconductor processing methods of making electrical contact to a node received within a mass of insulating dielectric material, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.
The prior problems associated with potential mask misalignment relative to simultaneous etching of four contacts will be readily appreciated from a description of the invention which follows.